VHDL Logbook

UART (The story of the shitty PL2303 cable)

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Spent a couple days writing a simple UART, everything looked good in the simulator.. so I went off and ordered another USB → RS232 dongle because I didn't have one to hand. After waiting a week or so for it to come from China I plugged it in and got loads of shit in minicom. I checked the simulation again, the waveform was perfect, timing was like .01% so perfectly within tolerances. After scratching my head for a while I tried a sample RS232 implementation for the board from Digilent, same result. I then jumpered the RX and TX pins on the cable, not a sausage; So not only is the receiver totally bust on this thing (I have a feeling it has something to do with the resonator and poor construction) the transmitter doesn't work at all! So I bought a ¥1500 FT232 board from AkizukiDenshi, worked first time. Moral of the story; Before you go taking your code apart to fix something check your simulation, if that's correct check any bits of crappy hardware you might have.

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VGA Generation

The documentation for the Nexys2 board is wrong in that it suggests that the “back porch” part of the signal comes after a second sync pulse.. this is wrong.

For generating VGA use the copy'n'paste guide below.. replace the timings with the timings for the mode you wish to generate (I'm generating 800×600@72hz currently as the native clock on the board is 50mhz). You can get these timings from the tinyvga.com page.. I've linked it on the front page of this wiki.

One thing that no where seems to mention is that during “horizontal and vertical” sync and “front porch and back porch” you should keep the red, green and blue signals low. I think someone on #electronics@freenode said this is how the monitor calibrates what is black.. I had it sort of working by just holding the lines low during hsync (I think the monitor uses the signal levels as some sort of extra sync) but I couldn't plot pixels on the screen at the positions I wanted. Holding the lines low during all the blanking parts of the waveform sorted it. It's possible it only needs to happen in the porches or something. But it worked for me. :)

Horizonal Timing

Horizonal Dots         640     640     640        
Vertical Scan Lines    350     400     480
Horiz. Sync Polarity   POS     NEG     NEG
A (us)                 31.77   31.77   31.77     Scanline time
B (us)                 3.77    3.77    3.77      Sync pulse lenght 
C (us)                 1.89    1.89    1.89      Back porch
D (us)                 25.17   25.17   25.17     Active video time
E (us)                 0.94    0.94    0.94      Front porch

         ______________________          ________
________|        VIDEO         |________| VIDEO (next line)
    |-C-|----------D-----------|-E-|
__   ______________________________   ___________
  |_|                              |_|
  |B|
  |---------------A----------------|

Vertical Timing

Horizonal Dots         640     640     640
Vertical Scan Lines    350     400     480
Vert. Sync Polarity    NEG     POS     NEG      
Vertical Frequency     70Hz    70Hz    60Hz
O (ms)                 14.27   14.27   16.68     Total frame time
P (ms)                 0.06    0.06    0.06      Sync length
Q (ms)                 1.88    1.08    1.02      Back porch
R (ms)                 11.13   12.72   15.25     Active video time
S (ms)                 1.2     0.41    0.35      Front porch

         ______________________          ________
________|        VIDEO         |________|  VIDEO (next frame)
    |-Q-|----------R-----------|-S-|
__   ______________________________   ___________
  |_|                              |_|
  |P|
  |---------------O----------------|

 
coding/vhdllogbook.txt · Last modified: 2010/02/18 15:01 by daniel
 
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